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Design, Test and Verification of RISC-V Architectures

Seminar in Computer Architecture

Pascal Raiola

Philipp M. Scholl

Bernd Becker

Summer Term 2020


The recent advent of the Open-Source RISC-V Instruction Set Architecture (ISA) [11] has fueled the development of novel processors [12] and related computer architectures. These developments present novel challenges and opportunities to design special- and general-purpose processors and integrate them into a single system, which is optimized for specific applications. Ranging from High-Performance Computing (HPC), to different accelerators for machine learning and scientific computing [13], and embedded or safety-critical applications [14], the cores can be scaled to differing applications. Such novel designs also demand streamlined testing and verification approaches.

In this seminar we review the current state-of-the-art in RISC-V research. A particular focus is on testing and verification approaches, but is not limited to that. The seminar is held online with short weekly update meetings. You are expected to work as a group towards the creation of a comprehensive review of RISC-V research and you will learn:

  • to present, and analyse scientific work to and with a group of fellow experts
  • to apply the peer review process to improve your own and the work of your peers
  • to extract, summarize and evaluate facts and scientific findings

Our goal is to prepare you for analysing related work in your writing and endeavours. This course is also an opportunity to find a master thesis topic in the area of RISC-V, which is part of the chair’s efforts in Germany’s Scale4Edge project. There are no prerequisites for this course, however the lectures on Verification of Digital Circuits and Computer Architecutre are helpful.

We will use BigBlueButton for our meetings:

Big Blue Button


The successful completion will be rewarded with 4 ECTS point, which amounts to around 120h of work. The examination consists of your active participation in weekly meetings, participation in the peer review process, a final 10-minute presentation and a written report of 4-6 pages in IEEE Conference format.

The course is limited to 20 participants, and you can work in groups of two.

The seminar is organized in six phases: allocation, bidding, research, peer review, revision, and presentation. Allocation is done via the hisinone system to register for the seminar. Afterwards the paper-bidding process allows you to record your topic preferences. Each participants will be assigned to one topic. The research phase allows you to work on your topic and write your report. The report is handed in during the semester for peer review, where participants are also asked to review the reports of their peers. According to your received reviews you revise your papers, which are to be handed in before the final presentation.

Date Topic Duration
May, 11th to May 20th Registration
May, 12th, 10:00 Seminar Presentation 30m
May, 20th Seat allocation
May, 25th, 23:59 Topic Bidding Ends
May, 28th, 10:00 Kickoff, Topic Distribution 30m
tue and thu, 10:00 until Jul, 28th 2min stand-ups 20m
Jul, 12th, 23:59 Paper Deadline
Jul, 13th, 23:59 Review Paper Bidding ends
Jul, 20th, 23:59 Review Deadline
Jul, 29th, 23:59 Revised Paper Deadline
Jul, 30th, 10:00 Final Presentation 2h

Written summary

The written summary should follow the form and the structure of a short scientific paper (conference paper). It starts with a title, the name of the author and an abstract, which succinctly describes the main results of the article. The first section is an introduction, which should motivate the argument of the article and arouse interest for the following material. The introduction must finish with an overview about the structure.

The main text will normally be divided into several numbered sections. There is a strict limitation of 6 pages. The participant should demonstrate his/her ability to understand a longer scientific text, to grasp the main points and to render them within the limitations of a specific number of pages. It is possible, though not mandatory, to give a critical valuation of the material and to point out a personal view. This should be kept within brief limits and should under no circumstances be mixed with the proper description of the argument. It should always be clear to the reader which part describes the author’s opinion and which part describes the scientific article.

The text has to end with a final section which should briefly (1–2 paragraphs) sum up the ideas of the article and if necessary give an outlook. Finally there is the References section.

The text can be written in English or German. Adhere to the IEEE Conference format. The 6-pages-limitation applies to the whole of the document, including title and references. The summary has to be submitted in pdf format. The 6-pages limitation must not be exceeded!

For further guidelines see the technical writing guide and the Chicago Manual of Style.


Prepare slides for you final presentation. The slides can be submitted in German or English, in power point/PDF/HTML. Test your presentation beforehand, and adhere to the 10-minute limitation. For non-trivial slides you can roughly estimate a 2-min presentation time.

The goal of the presentation is to give the participants the frame to understand the topic, the problem, the achievements and open questions. Formal deductions should be used scarcely and if possible should be visualized (but without compromising the correctness of the written parts). Longer sentences (more than 2 lines) should be avoided if possible. Ideally, you should use short, succinct, incomplete sentences with enumerations. The presentation should not be a mere reading of your written slides.

At the end of the presentation, summarize (1–2 slides) your talk. A final slide (“Any questions?”, “That’s all folks!”, pictures of pets and so on) is usually not a good foundation for a discussion, a summary is preferable.

List of topics and participants

Topics Supervisor Student(s)
. RISC-V Vector Processor [1], [15], [16] Linus Feiten Monideep Bora & Parik Shith
. Concolic (Software) Testing: A RISC-V Case Study [3] Tobias Paxian Nadja Gahl & Markus Schwörer
. Software-based Self-Test of Microprocessors (Overview) [6], [9] Benjamin Völker Tobias Faller
. Reconfigurable Scan Networks (Overview) [10], [5] Pascal Raiola Redon Prekazi & Nita Bukoshi
. Secure Data Transfer in Reconfigurable Scan Networks [7], [8] Pascal Raiola Niklas Steinwachs
. Formal Methods for Test Generation [2], [4] Leonore Winterer Faisal Omari & Egemen Öz
: Topic List


[1] Matheus A. Cavalcante, Fabian Schuiki, Florian Zaruba, Michael Schaffner, and Luca Benini. 2020. Ara: A 1-ghz+ scalable and energy-efficient RISC-V vector processor with multiprecision floating-point support in 22-nm FD-SOI. IEEE Trans. Very Large Scale Integr. Syst. 28, 2 (2020), 530–543. DOI:https://doi.org/10.1109/TVLSI.2019.2950087

[2] Sankar Gurumurthy, Shobha Vasudevan, and Jacob A. Abraham. 2006. Automatic generation of instruction sequences targeting hard-to-detect structural faults in a processor. In 2006 IEEE international test conference, ITC 2006, santa clara, ca, usa, october 22-27, 2006, IEEE Computer Society, 1–9. DOI:https://doi.org/10.1109/TEST.2006.297676

[3] Vladimir Herdt, Daniel Große, Hoang M. Le, and Rolf Drechsler. 2019. Early concolic testing of embedded binaries with virtual prototypes: A RISC-V case study. In Proceedings of the 56th annual design automation conference 2019, DAC 2019, las vegas, nv, usa, june 02-06, 2019, ACM, 188. DOI:https://doi.org/10.1145/3316781.3317807

[4] Loganathan Lingappan and Niraj K. Jha. 2007. Satisfiability-based automatic test program generation and design for testability for microprocessors. IEEE Trans. Very Large Scale Integr. Syst. 15, 5 (2007), 518–530. DOI:https://doi.org/10.1109/TVLSI.2007.896908

[5] Michele Portolan. 2016. A novel test generation and application flow for functional access to IEEE 1687 instruments. In 21th IEEE european test symposium, ETS 2016, amsterdam, netherlands, may 23-27, 2016, IEEE, 1–6. DOI:https://doi.org/10.1109/ETS.2016.7519302

[6] Mihalis Psarakis, Dimitris Gizopoulos, Edgar E. Sánchez, and Matteo Sonza Reorda. 2010. Microprocessor software-based self-testing. IEEE Design & Test of Computers 27, 3 (2010), 4–19. DOI:https://doi.org/10.1109/MDT.2010.5

[7] Pascal Raiola, Michael A. Kochte, Ahmed Atteya, Laura Rodríguez Gòmez, Hans-Joachim Wunderlich, Bernd Becker, and Matthias Sauer. 2018. Detecting and resolving security violations in reconfigurable scan networks. In 24th IEEE international symposium on on-line testing and robust system design, IOLTS 2018, platja d’Aro, spain, july 2-4, 2018, IEEE, 91–96. DOI:https://doi.org/10.1109/IOLTS.2018.8474188

[8] Pascal Raiola, Benjamin Thiemann, Jan Burchard, Ahmed Atteya, Natalia Lylina, Hans-Joachim Wunderlich, Bernd Becker, and Matthias Sauer. 2019. On secure data flow in reconfigurable scan networks. In Design, automation & test in europe conference & exhibition, DATE 2019, florence, italy, march 25-29, 2019, IEEE, 1016–1021. DOI:https://doi.org/10.23919/DATE.2019.8715172

[9] Andreas Riefert, Riccardo Cantoro, Matthias Sauer, Matteo Sonza Reorda, and Bernd Becker. 2016. A flexible framework for the automatic generation of SBST programs. IEEE Trans. Very Large Scale Integr. Syst. 24, 10 (2016), 3055–3066. DOI:https://doi.org/10.1109/TVLSI.2016.2538800

[10] Farrokh Ghani Zadegan, Erik Larsson, Artur Jutman, Sergei Devadze, and Rene Krenz-Baath. 2014. Design, verification, and application of IEEE 1687. In 23rd IEEE asian test symposium, ATS 2014, hangzhou, china, november 16-19, 2014, IEEE Computer Society, 93–100. DOI:https://doi.org/10.1109/ATS.2014.28

[11] The Risc-V Foundation. Retrieved from https://riscv.org/

[12] RISC-V Cores and SoC Overview. Retrieved from https://riscv.org/risc-v-cores/

[13] European Processor Initiative Overview. Retrieved from https://www.european-processor-initiative.eu/accelerator/

[14] The PULP Platform. Retrieved from https://pulp-platform.org/

[16] Retrieved from https://youtu.be/F66F1nT1T8oURL